The present invention relates to a technique effectively applied to a layout technology of a power semiconductor device (or semiconductor integrated circuit device).
Japanese Unexamined Patent Publication No. 2006-228882 (Patent Document 1) discloses a technique for avoiding undesired etching of an interlayer insulating film from its side by burying an integral polysilicon strip intersecting a word line when forming a polysilicon burying a contact in a dynamic random access memory (DRAM) chip.
Japanese Unexamined Patent Publication No. 2006-54483 (Patent Document 2) discloses a gate electrode having a structure with an inside region thereof removed in a planar vertical power MOSFET for the purpose of reduction in gate capacitance.